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@OpenXiangShan

XiangShan

Open-source high-performance RISC-V processor

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  1. XiangShan XiangShan Public

    Open-source high-performance RISC-V processor

    Scala 7.3k 948

  2. XiangShan-doc XiangShan-doc Public

    Documentation for XiangShan

    Markdown 445 152

  3. HuanCun HuanCun Public

    Open-source high-performance non-blocking cache

    Scala 101 39

  4. difftest difftest Public

    Modern co-simulation framework for RISC-V CPUs

    C++ 186 109

  5. xs-env xs-env Public

    XiangShan Frontend Develop Environment

    Shell 73 76

  6. NEMU NEMU Public

    Super fast RISC-V ISA emulator for XiangShan processor

    C 352 145

Repositories

Showing 10 of 107 repositories
  • GEM5 Public
    OpenXiangShan/GEM5's past year of commit activity
    C++ 160 BSD-3-Clause 92 30 100 Updated Sep 27, 2026
  • XiangShan-doc Public

    Documentation for XiangShan

    OpenXiangShan/XiangShan-doc's past year of commit activity
    Markdown 445 CC-BY-4.0 152 7 1 Updated Sep 27, 2026
  • XiangShan Public

    Open-source high-performance RISC-V processor

    OpenXiangShan/XiangShan's past year of commit activity
    Scala 7,274 MulanPSL-2.0 948 119 168 Updated Sep 27, 2026
  • XSCache Public

    Open-source L2 (RN) & LLC (HN) cache for XiangShan open-source RISC-V core. Supports CHI Issue B/C/E.b protocols.

    OpenXiangShan/XSCache's past year of commit activity
    Scala 0 7 0 6 Updated Sep 27, 2026
  • difftest Public

    Modern co-simulation framework for RISC-V CPUs

    OpenXiangShan/difftest's past year of commit activity
    C++ 186 MulanPSL-2.0 109 8 16 Updated Sep 27, 2026
  • OpenXiangShan/XiangShan-Dashboard's past year of commit activity
    Vue 2 0 0 1 Updated Sep 26, 2026
  • gsim Public
    OpenXiangShan/gsim's past year of commit activity
    C++ 84 12 2 8 Updated Sep 26, 2026
  • NEMU Public

    Super fast RISC-V ISA emulator for XiangShan processor

    OpenXiangShan/NEMU's past year of commit activity
    C 352 145 40 41 Updated Sep 25, 2026
  • AME_gem5 Public
    OpenXiangShan/AME_gem5's past year of commit activity
    C++ 5 BSD-3-Clause 2 0 0 Updated Sep 24, 2026
  • XiangShanLab Public

    XiangShanLab is the open-source XiangShan ecosystem's entry layer — a learning, practice, and collaboration hub spanning the RISC-V processor core and its specialized domains, making high-performance processor design learnable, doable, and participable, and welcoming collaborators from academia and industry to join real open-source development.

    OpenXiangShan/XiangShanLab's past year of commit activity
    Scala 41 23 49 1 Updated Sep 24, 2026