IMX900 with RG12 format only works with modified pix_clk_hz

[heikohimu]

It seems that the calculation of cil_settletime based on pix_clk_hz does only work with 10 bit format, but not with 12 bit. Here is what we found out and the workaround for getting it to work.

We are using VC mipi modules with the IMX900 on an Orin Nano Nano 8GB with a custom baseboard with Jetpack 6 (36.5.0) and configured it to use 4 lanes. With RG10 format, streaming of images works fine. We are using the video4linux interface for streaming. However, switching to RG12 (and reducing the maximum framerate to 67 Hz) does not work, i.e. there are no images coming. Switching to 2 lanes does not help. Grabbing waits forever. Tested with v4l2-ctl.

When enabling tracing, we see that there is no data coming from the cameras:

$ sudo cat /sys/kernel/debug/tracing/trace
# tracer: nop
#
# entries-in-buffer/entries-written: 31/31   #P:6
#
#                                _-------=> irqs-off
#                               / _------=> need-resched
#                              | / _-----=> need-resched-lazy
#                              || / _----=> hardirq/softirq
#                              ||| / _---=> preempt-depth
#                              |||| / _--=> preempt-lazy-depth
#                              ||||| / _-=> migrate-disable
#                              |||||| /     delay
#           TASK-PID     CPU#  |||||||  TIMESTAMP  FUNCTION
#              | |         |   |||||||      |         |
        v4l2-ctl-15054   [001] .......  1826.250892: tegra_channel_open: vi-output, vc_mipi 7-001a
        v4l2-ctl-15054   [001] .......  1826.259253: tegra_channel_set_power: vc_mipi 7-001a : 0x1
        v4l2-ctl-15054   [001] .......  1826.259258: camera_common_s_power: status : 0x1
        v4l2-ctl-15054   [001] .......  1826.259267: tegra_channel_set_power: 13e00000.host1x:nvcsi@15a00000- : 0x1
        v4l2-ctl-15054   [001] .......  1826.259269: csi_s_power: enable : 0x1
        v4l2-ctl-15054   [001] .......  1826.259792: tegra_channel_capture_setup: vnc_id 0 W 2048 H 1536 fmt c4
 vi-output, vc_m-15055   [002] .......  1826.269668: vi_task_submit: class_id:48 ch:0 syncpt_id:8 syncpt_thresh:2000 pid:15055 tid:15055
 vi-output, vc_m-15055   [002] .......  1826.269675: vi_task_submit: class_id:48 ch:0 syncpt_id:8 syncpt_thresh:2000 pid:15055 tid:15055
 vi-output, vc_m-15055   [002] .......  1826.269677: vi_task_submit: class_id:48 ch:0 syncpt_id:8 syncpt_thresh:2000 pid:15055 tid:15055
 vi-output, vc_m-15055   [002] .......  1826.269678: vi_task_submit: class_id:48 ch:0 syncpt_id:8 syncpt_thresh:2000 pid:15055 tid:15055
        v4l2-ctl-15054   [001] .......  1826.269708: tegra_channel_set_stream: enable : 0x1
        v4l2-ctl-15054   [001] .......  1826.271568: tegra_channel_set_stream: 13e00000.host1x:nvcsi@15a00000- : 0x1
        v4l2-ctl-15054   [001] .......  1826.271570: csi_s_stream: enable : 0x1
        v4l2-ctl-15054   [001] .......  1826.271962: tegra_channel_set_stream: vc_mipi 7-001a : 0x1

After interrupting grabbing with CTRL-C:

        v4l2-ctl-15054   [001] .......  1860.481537: tegra_channel_close: vi-output, vc_mipi 7-001a
 vi-output, vc_m-15056   [003] .......  1860.481561: tegra_channel_capture_frame: sof:0.0
 vi-output, vc_m-15056   [003] .......  1860.481563: tegra_channel_capture_frame: eof:0.0
 vi-output, vc_m-15056   [003] .......  1860.481568: tegra_channel_capture_frame: sof:0.0
 vi-output, vc_m-15056   [003] .......  1860.481569: tegra_channel_capture_frame: eof:0.0
 vi-output, vc_m-15056   [003] .......  1860.481570: tegra_channel_capture_frame: sof:0.0
 vi-output, vc_m-15056   [003] .......  1860.481571: tegra_channel_capture_frame: eof:0.0
 vi-output, vc_m-15056   [003] .......  1860.481572: tegra_channel_capture_frame: sof:0.0
 vi-output, vc_m-15056   [003] .......  1860.481573: tegra_channel_capture_frame: eof:0.0
        v4l2-ctl-15054   [001] .......  1860.481584: tegra_channel_set_stream: enable : 0x0
        v4l2-ctl-15054   [001] .......  1860.481585: tegra_channel_set_stream: vc_mipi 7-001a : 0x0
        v4l2-ctl-15054   [001] .......  1860.532243: tegra_channel_set_stream: 13e00000.host1x:nvcsi@15a00000- : 0x0
        v4l2-ctl-15054   [001] .......  1860.532246: csi_s_stream: enable : 0x0
        v4l2-ctl-15054   [001] .......  1860.535457: tegra_channel_set_power: vc_mipi 7-001a : 0x0
        v4l2-ctl-15054   [001] .......  1860.535462: camera_common_s_power: status : 0x0
        v4l2-ctl-15054   [001] .......  1860.535471: tegra_channel_set_power: 13e00000.host1x:nvcsi@15a00000- : 0x0
        v4l2-ctl-15054   [001] .......  1860.535473: csi_s_power: enable : 0x0

dmesg shows that the rate is 1485 for all formats and number of lanes:

[   13.637578] i2c 2-0010: +--- Module Modes -------+---------+---------+---------+
[   13.637579] i2c 2-0010: |  # | rate    | lanes   | format  | type    | binning |
[   13.637579] i2c 2-0010: +----+---------+---------+---------+---------+---------+
[   13.637582] i2c 2-0010: |  0 |    1485 |       2 | RAW08   | STREAM  |       0 |
[   13.637584] i2c 2-0010: |  1 |    1485 |       2 | RAW10   | STREAM  |       0 |
[   13.637586] i2c 2-0010: |  2 |    1485 |       2 | RAW12   | STREAM  |       0 |
[   13.637588] i2c 2-0010: |  3 |    1485 |       2 | RAW08   | EXT.TRG |       0 |
[   13.637590] i2c 2-0010: |  4 |    1485 |       2 | RAW10   | EXT.TRG |       0 |
[   13.637591] i2c 2-0010: |  5 |    1485 |       2 | RAW12   | EXT.TRG |       0 |
[   13.637592] i2c 2-0010: |  6 |    1485 |       4 | RAW08   | STREAM  |       0 |
[   13.637593] i2c 2-0010: |  7 |    1485 |       4 | RAW10   | STREAM  |       0 |
[   13.637595] i2c 2-0010: |  8 |    1485 |       4 | RAW12   | STREAM  |       0 |
[   13.637596] i2c 2-0010: |  9 |    1485 |       4 | RAW08   | EXT.TRG |       0 |
[   13.637597] i2c 2-0010: | 10 |    1485 |       4 | RAW10   | EXT.TRG |       0 |
[   13.637599] i2c 2-0010: | 11 |    1485 |       4 | RAW12   | EXT.TRG |       0 |
[   13.637600] i2c 2-0010: +----+---------+---------+---------+---------+---------+

According to our research and experiments, cil_settletime is calculated wrong and this prevents receiving data from the camera. However, we found a workaround for this problem, because the settle time calculation is based on pix_clk_hz value. Changing that by the factor 10/used_bitdepth works. We set the pix_clk_hz value in the device tree to 500000000 and now streaming with RG12 works fine.

I do not know if this is specific for IMX900 and what would be the best way to fix it.

[bazo80]

Hello @heikohimu ,

we are about to create a more detailled description regarding to the pix_clk_hz parameter. Basically there is no need to adjust the cil_settletime but the pix_clk_hz value:

Lane * MBit / bit-depth would give a better value:
4*1485000000 / 12 = 495000000

That means
pix_clk_hz = "495000000";
would fit better into your scenario.

best regards