All pull requests

Pull requests

• [Examples] Run example programs as smoke tests in CI

  #1435·mumallaeng opened Sep 22, 2026·

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  4

• [RouterHelper] getSourceToSinkINTNodeDelays() only for fully routed

  #1434·eddieh-xlnx opened Sep 21, 2026Collaborator·

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  2

• [CodePerfTracker] Only track OS memory usage on Linux

  #1433·mumallaeng opened Sep 20, 2026·

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  1

• [TestDesign] Add test{Add,Create}SiteInstDuplicate()

  needs new release
  #1432·eddieh-xlnx opened Sep 18, 2026Collaborator·

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• [DesignTools] Improve createMissingSitePinInsts()

  #1429·eddieh-xlnx opened Sep 18, 2026Collaborator·

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• [TestSiteInst] Add testGetSiteWireIndicesFromNetRoundTripsWithinSiteWireCount()

  needs new release
  #1428·eddieh-xlnx opened Sep 18, 2026Collaborator·

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• [TestSitePinInst] Add testSetRoutedTracksSiteInstChanges()

  needs new release
  #1427·eddieh-xlnx opened Sep 18, 2026Collaborator·

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• [TestNet] Check name changes invalidate cached logical hier net

  needs new release
  #1425·eddieh-xlnx opened Sep 16, 2026Collaborator·

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• [DesignTools] Rework populateBlackBox() batching, net merging, and reporting

  #1424·eddieh-xlnx opened Sep 16, 2026Collaborator·

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• Add SDF parser, writer, and timing graph annotator

  #1419·clavin-xlnx opened Sep 2, 2026Member·

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  2

• [TestDesign] Add testTrack{SiteInst,Net}Changes()

  needs new release
  #1411·eddieh-xlnx opened Aug 31, 2026Collaborator·

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• [TestCell] Add testUpdateNameResetsLogicalInst()

  needs new release
  #1409·eddieh-xlnx opened Aug 31, 2026Collaborator·

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• ModuleInst: reject placements landing on depopulated SLL UBUMP nodes

  #1401·andrewb1999 opened Aug 4, 2026Contributor·

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  3

• Add PBlockStaticNetFixer to Simplify Relocation of Vivado Routed Modules

  #1400·andrewb1999 opened Aug 4, 2026Contributor·

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  12

• Test for module relocation in modular SLRs

  needs new release
  #1399·clavin-xlnx opened Jul 30, 2026Member·

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• [EDIFNetlist] NetlistValidator - A tool for checking output EDIF for inconsistencies before they are found on Vivado import

  #1387·clavin-xlnx opened Jun 25, 2026Member·

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• Enumerate Versal Delay Paths [No timing information]

  #1371·clavin-xlnx opened May 21, 2026Member·

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• Add backward routing for RapidWright.

  #1346·kylepham-amd opened Jan 7, 2026Contributor·

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  9

• Fix DesignTools.getConnectionPips for sinks driven by lut constant generators

  #1231·reillymck opened Jun 20, 2025Contributor·

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  5

• Example Clock Signal Tracer

  #1216·clavin-xlnx opened Jun 12, 2025Member·

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• [TestExamples] Test PipelineGenerator with Vivado

  #1193·eddieh-xlnx opened May 20, 2025Collaborator·

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• [EDIFNetlist] exportEDIF() to use getLibrariesInExportOrder()

  #1148·eddieh-xlnx opened Feb 14, 2025Collaborator·

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  1

• [DREAMPlaceFPGA] Add placeDesign() wrapper for DREAMPlaceFPGA

  #1137·eddieh-xlnx opened Jan 13, 2025Collaborator·

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  1

• [RWRoute] Adjust wire base costs + cross SLR estimates

  #1030·eddieh-xlnx opened Jul 12, 2024Collaborator·

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  1

• [Interchange] Exports DeviceResources Routing (Wires and Nodes) Info in Multiple Messages

  #1017·clavin-xlnx opened Jun 25, 2024Member·

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