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  1. riscv-npu-soc riscv-npu-soc Public

    A complete RISC-V SoC in SystemVerilog: pipelined CPU + memory-mapped systolic-array NPU accelerator, running real firmware that offloads a matrix multiply. Includes a small RV32I assembler. Self-c…

    SystemVerilog 4

  2. riscv-rv32i-pipeline riscv-rv32i-pipeline Public

    A 5-stage pipelined RV32I RISC-V processor in SystemVerilog: data forwarding, load-use stalls, branch flush. Runs a real program; self-checking testbench (11/11) + CI.

    SystemVerilog 1

  3. dms-tinyml-soc dms-tinyml-soc Public

    A Driver-Monitoring TinyML system-on-chip: RISC-V CPU + a quantized neural-network accelerator that classifies driver state (ALERT/DROWSY/DISTRACTED). Full train->quantize->silicon->verify flow. Se…

    SystemVerilog 1

  4. apex-safety-fsm apex-safety-fsm Public

    RTL safety supervisor (SystemVerilog): an emergency-stop preempts the on-chip AI from any state and latches until a human clears it. From my APEX FPGA autonomous-vehicle SoC (SJSU EE277). Self-chec…

    SystemVerilog

  5. fpga-qos-scheduler fpga-qos-scheduler Public

    Parameterized fixed-priority, non-preemptive task scheduler in SystemVerilog with a hardware safety-deadline monitor. Self-checking testbench + CI. RTL counterpart to my APEX FPGA SoC.

    SystemVerilog

  6. efedemi efedemi Public

    Profile README