The Institute for Complex Systems (ICS) targets the ever-increasing complexity of hardware/software systems. Here, the institute considers suitable abstraction levels, i.e. Virtual Prototypes (VPs) in SystemC for HW/SW systems at the Electronic System Level (ESL), HW designs in Verilog/VHDL at the Register Transfer Level (RTL), down to the gate-level. Primary research areas are verification, debugging, and synthesis, all major problems in Electronic Design Automation (EDA). We heavily use the RISC-V ISA in our research work (see e.g. our open-source RISC-V VP++).
Institute for Complex Systems (ICS), Johannes Kepler University Linz
ICS conducts research in EDA with focus on verification, debugging, and synthesis; abstraction levels: SystemC virtual prototypes, RTL downto gate-level.
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riscv-vp-plusplus
riscv-vp-plusplus PublicRISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute for Complex Systems, Johannes Kepler University, Linz.
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- riscv-vp-plusplus Public
RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute for Complex Systems, Johannes Kepler University, Linz.
- RVVTS Public
RVVTS is a Python framework for generating, running, minimizing, and analyzing RISC-V Vector implementation tests.
- RVVTS_SailRV_Spike Public
This repository contains the RVVTS test sets, reports, and categorized failure cases discussed in the paper "Sail-RISC-V and Spike for RISC-V Vector: Toward Consistent Golden Reference Behavior" by Manfred Schlägl, Katharina Ruep, and Daniel Große, presented at RISC-V Summit Europe 2026.
- RVVTS_SailRV_Tester Public
Automated setup, execution, and report generation for RVVTS-based Sail-RISC-V vs. Spike regression testing.
- FP-RVVTS Public
This repository contains FP-RVVTS test sets, reports, and categorized failure cases for Sail RISC-V vs. floating-point designs under test (DUTs) discussed in the paper "FP-RVVTS: Sail-guided Verification of RISC-V Floating-Point Implementations" by Katharina Ruep, Manfred Schlägl, and Daniel Große.
- RVVTS_RTL_AFC_Ara Public
This repository contains the RVVTS test sets, reports, and categorized failures for PULP Ara discussed in the paper "From Generation to Failure Categorization: An Open-Source automated RTL Verification Framework for RVV" by Manfred Schlägl, Jonas Reichhardt, and Daniel Große, presented at GLSVLSI 2026.
- cheri-exploits Public
Collection of tests and exploits for CHERI targeted for execution on RISC-V VP++.
- GUI-VP_Kit Public
Quick-to-create and easy-to-use platform for experimentation with Linux on the open-source SystemC RISC-V based virtual prototype RISC-V VP++
- RVVRadar Public Forked from mschlaegl/RVVRadar
RVVRadar is a framework to support the programmer over the four major steps of development, verification, measurement and evaluation during the vectorization process of algorithms for the RISC-V Vector extension (RVV).
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